CUdevice_attribute_enum

Device properties

Values

ValueMeaning
CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_BLOCK1
CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_X2

< Maximum number of threads per block

CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Y3

< Maximum block dimension X

CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Z4

< Maximum block dimension Y

CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_X5

< Maximum block dimension Z

CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Y6

< Maximum grid dimension X

CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Z7

< Maximum grid dimension Y

CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK8

< Maximum grid dimension Z

CU_DEVICE_ATTRIBUTE_SHARED_MEMORY_PER_BLOCK8

< Maximum shared memory available per block in bytes

CU_DEVICE_ATTRIBUTE_TOTAL_CONSTANT_MEMORY9

< Deprecated, use CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK

CU_DEVICE_ATTRIBUTE_WARP_SIZE10

< Memory available on device for __constant__ variables in a CUDA C kernel in bytes

CU_DEVICE_ATTRIBUTE_MAX_PITCH11

< Warp size in threads

CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK12

< Maximum pitch in bytes allowed by memory copies

CU_DEVICE_ATTRIBUTE_REGISTERS_PER_BLOCK12

< Maximum number of 32-bit registers available per block

CU_DEVICE_ATTRIBUTE_CLOCK_RATE13

< Deprecated, use CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK

CU_DEVICE_ATTRIBUTE_TEXTURE_ALIGNMENT14

< Typical clock frequency in kilohertz

CU_DEVICE_ATTRIBUTE_GPU_OVERLAP15

< Alignment requirement for textures

CU_DEVICE_ATTRIBUTE_MULTIPROCESSOR_COUNT16

< Device can possibly copy memory and execute a kernel concurrently. Deprecated. Use instead CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT.

CU_DEVICE_ATTRIBUTE_KERNEL_EXEC_TIMEOUT17

< Number of multiprocessors on device

CU_DEVICE_ATTRIBUTE_INTEGRATED18

< Specifies whether there is a run time limit on kernels

CU_DEVICE_ATTRIBUTE_CAN_MAP_HOST_MEMORY19

< Device is integrated with host memory

CU_DEVICE_ATTRIBUTE_COMPUTE_MODE20

< Device can map host memory into CUDA address space

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_WIDTH21

< Compute mode (See ::CUcomputemode for details)

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_WIDTH22

< Maximum 1D texture width

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_HEIGHT23

< Maximum 2D texture width

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH24

< Maximum 2D texture height

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT25

< Maximum 3D texture width

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH26

< Maximum 3D texture height

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH27

< Maximum 3D texture depth

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT28

< Maximum 2D layered texture width

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS29

< Maximum 2D layered texture height

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_WIDTH27

< Maximum layers in a 2D layered texture

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_HEIGHT28

< Deprecated, use CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_NUMSLICES29

< Deprecated, use CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT

CU_DEVICE_ATTRIBUTE_SURFACE_ALIGNMENT30

< Deprecated, use CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS

CU_DEVICE_ATTRIBUTE_CONCURRENT_KERNELS31

< Alignment requirement for surfaces

CU_DEVICE_ATTRIBUTE_ECC_ENABLED32

< Device can possibly execute multiple kernels concurrently

CU_DEVICE_ATTRIBUTE_PCI_BUS_ID33

< Device has ECC support enabled

CU_DEVICE_ATTRIBUTE_PCI_DEVICE_ID34

< PCI bus ID of the device

CU_DEVICE_ATTRIBUTE_TCC_DRIVER35

< PCI device ID of the device

CU_DEVICE_ATTRIBUTE_MEMORY_CLOCK_RATE36

< Device is using TCC driver model

CU_DEVICE_ATTRIBUTE_GLOBAL_MEMORY_BUS_WIDTH37

< Peak memory clock frequency in kilohertz

CU_DEVICE_ATTRIBUTE_L2_CACHE_SIZE38

< Global memory bus width in bits

CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_MULTIPROCESSOR39

< Size of L2 cache in bytes

CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT40

< Maximum resident threads per multiprocessor

CU_DEVICE_ATTRIBUTE_UNIFIED_ADDRESSING41

< Number of asynchronous engines

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_WIDTH42

< Device shares a unified address space with the host

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_LAYERS43

< Maximum 1D layered texture width

CU_DEVICE_ATTRIBUTE_CAN_TEX2D_GATHER44

< Maximum layers in a 1D layered texture

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_WIDTH45

< Deprecated, do not use.

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_HEIGHT46

< Maximum 2D texture width if CUDA_ARRAY3D_TEXTURE_GATHER is set

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH_ALTERNATE47

< Maximum 2D texture height if CUDA_ARRAY3D_TEXTURE_GATHER is set

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT_ALTERNATE48

< Alternate maximum 3D texture width

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH_ALTERNATE49

< Alternate maximum 3D texture height

CU_DEVICE_ATTRIBUTE_PCI_DOMAIN_ID50

< Alternate maximum 3D texture depth

CU_DEVICE_ATTRIBUTE_TEXTURE_PITCH_ALIGNMENT51

< PCI domain ID of the device

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_WIDTH52

< Pitch alignment requirement for textures

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_WIDTH53

< Maximum cubemap texture width/height

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_LAYERS54

< Maximum cubemap layered texture width/height

CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_WIDTH55

< Maximum layers in a cubemap layered texture

CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_WIDTH56

< Maximum 1D surface width

CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_HEIGHT57

< Maximum 2D surface width

CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_WIDTH58

< Maximum 2D surface height

CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_HEIGHT59

< Maximum 3D surface width

CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_DEPTH60

< Maximum 3D surface height

CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_WIDTH61

< Maximum 3D surface depth

CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_LAYERS62

< Maximum 1D layered surface width

CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_WIDTH63

< Maximum layers in a 1D layered surface

CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_HEIGHT64

< Maximum 2D layered surface width

CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_LAYERS65

< Maximum 2D layered surface height

CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_WIDTH66

< Maximum layers in a 2D layered surface

CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_WIDTH67

< Maximum cubemap surface width

CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_LAYERS68

< Maximum cubemap layered surface width

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LINEAR_WIDTH69

< Maximum layers in a cubemap layered surface

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_WIDTH70

< Maximum 1D linear texture width

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_HEIGHT71

< Maximum 2D linear texture width

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_PITCH72

< Maximum 2D linear texture height

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_WIDTH73

< Maximum 2D linear texture pitch in bytes

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_HEIGHT74

< Maximum mipmapped 2D texture width

CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR75

< Maximum mipmapped 2D texture height

CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR76

< Major compute capability version number

CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_MIPMAPPED_WIDTH77

< Minor compute capability version number

CU_DEVICE_ATTRIBUTE_STREAM_PRIORITIES_SUPPORTED78

< Maximum mipmapped 1D texture width

CU_DEVICE_ATTRIBUTE_GLOBAL_L1_CACHE_SUPPORTED79

< Device supports stream priorities

CU_DEVICE_ATTRIBUTE_LOCAL_L1_CACHE_SUPPORTED80

< Device supports caching globals in L1

CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_MULTIPROCESSOR81

< Device supports caching locals in L1

CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_MULTIPROCESSOR82

< Maximum shared memory available per multiprocessor in bytes

CU_DEVICE_ATTRIBUTE_MANAGED_MEMORY83

< Maximum number of 32-bit registers available per multiprocessor

CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD84

< Device can allocate managed memory on this system

CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD_GROUP_ID85

< Device is on a multi-GPU board

CU_DEVICE_ATTRIBUTE_MAX86

< Unique id for a group of devices on the same multi-GPU board

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